1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising an embedded strain-inducing semiconductor material and a high-k metal gate electrode structure formed in an early manufacturing stage.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistors, which represent the dominant circuit elements in complex integrated circuits. For example, several hundred million transistors may be provided in presently available complex integrated circuits, wherein performance of the transistors in the speed critical signal paths substantially determines overall performance of the integrated circuit. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, the complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface positioned between highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
When reducing the channel length of field effect transistors, generally an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high speed transistor elements, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, in some approaches, the inferior controllability of the channel region of the short channel transistors caused by the continuous reduction of the critical dimensions of gate electrode structures has been addressed by an appropriate adaptation of the material composition of the gate dielectric material.
To this end, it has been proposed that, for a physically appropriate thickness of a gate dielectric material, i.e., for a thickness resulting in an acceptable level of gate leakage currents, a desired high capacitive coupling may be achieved by using appropriate material systems, which have a significantly higher dielectric constant compared to the conventionally used silicon dioxide-based materials. For example, dielectric materials including hafnium, zirconium, aluminum and the like may have a significantly higher dielectric constant and are therefore referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher when measured in accordance with typical measurement techniques. As is well known, the electronic characteristics of the transistors also strongly depend on the work function of the gate electrode material, which in turn influences the band structure of the semiconductor material in the channel regions separated from the gate electrode material by the gate dielectric layer. In well-established polysilicon/silicon dioxide-based gate electrode structures, the corresponding threshold voltage that is strongly influenced by the gate dielectric material and the adjacent electrode material is adjusted by appropriately doping the polysilicon material in order to appropriately adjust the work function of the polysilicon material at the interface between the gate dielectric material and the electrode material. Similarly, in gate electrode structures including a high-k gate dielectric material, the work function has to be appropriately adjusted for N-channel transistors and P-channel transistors, respectively, which may require appropriately selected work function adjusting metal species, such as lanthanum for N-channel transistors and aluminum for P-channel transistors and the like. For this reason, corresponding metal-containing conductive materials may be positioned close to the high-k gate dielectric material in order to form an appropriately designed interface that results in the target work function of the gate electrode structure. In some conventional approaches, the work function adjustment is performed at a very late manufacturing stage, i.e., after any high temperature processes, after which a placeholder material of the gate electrode structures, such as polysilicon, is replaced by an appropriate work function adjusting species in combination with an electrode metal, such as aluminum and the like. In this case, however, very complex patterning and deposition process sequences are required in the context of gate electrode structures having critical dimensions of 50 nm and significantly less, which may result in severe variations of the resulting transistor characteristics.
Therefore, other process strategies have been proposed in which the work function adjusting materials may be applied in an early manufacturing stage, i.e., upon forming the gate electrode structures, wherein the metal species may be thermally stabilized and encapsulated in order to obtain the desired work function and thus threshold voltage of the transistors without being unduly influenced by the further processing. It turns out that, for any appropriate metal species and metal-containing electrode materials, an appropriate adaptation of the band gap of the channel semiconductor material may be required, for instance in the P-channel transistors, in order to appropriately set the work function thereof. For this reason, frequently, a so-called threshold adjusting semiconductor material, for instance in the form of a silicon/germanium mixture, is formed on the active regions of the P-channel transistors prior to forming the gate electrode structures, thereby obtaining the desired offset in the band gap of the channel semiconductor material.
The threshold adjusting semiconductor material is typically formed selectively on the silicon-based active region of the P-channel transistors while masking the active region of the N-channel transistors by an appropriate mask material, such as silicon dioxide, silicon nitride and the like. In a selective epitaxial growth process, the process parameters, such as temperature, gas flow rates and the like, are established in such a manner that a significant material deposition may be restricted to crystalline surface areas, thereby forming increasingly a silicon/germanium mixture on the silicon base material, wherein a germanium concentration, the germanium gradient in the growth direction and the finally obtained thickness in the silicon/germanium layer may thus determine the finally obtained threshold voltage for otherwise given transistor parameters. Thereafter, the gate electrode structures are formed by using high-k dielectric materials in combination with appropriate metal-containing cap layers and work function adjusting metal species, which may be incorporated into the high-k material and/or the metal-containing cap layers in order to obtain appropriate work functions and thus threshold voltages for the P-channel transistors and the N-channel transistors, respectively. In this manner, sophisticated high-k metal gate electrode structures may be provided in an early manufacturing stage, thereby avoiding a complex process strategy as required by the so-called replacement gate approach.
It is well known that, in view of enhancing overall performance of sophisticated transistors, also various strain engineering techniques are typically applied, since creating a specific type of strain in the channel region of silicon-based transistors may result in a significant increase of the charge carrier mobility, which in turn translates into superior current drive capability and thus switching speed. A plurality of strategies have thus been developed, for instance providing highly stressed layers above the completed transistor structures, providing strain-inducing sidewall spacer structures, embedding strain-inducing semiconductor alloys, such as silicon/germanium, silicon/carbon and the like, into drain and source areas of the transistors, while in other approaches, in addition to or alternatively, also globally strained semiconductor base materials may be used.
In particular, the incorporation of a strain-inducing silicon/germanium material into the active regions of P-channel transistors is a very efficient strain-inducing mechanism which, however, may interact with the threshold voltage adjusting semiconductor alloy, as will be described in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 in a manufacturing stage in which a plurality of gate electrode structures 160A, 160B, 160C are formed on the active region 102A, in and above which a plurality of P-channel transistors 150A, 150B, 150C are to be formed. The active region 102A is to be understood as a part of a silicon-based semiconductor layer 102, which in turn is formed above an appropriate substrate 101, such as a silicon substrate and the like. The semiconductor layer 102, which is initially provided in the form of a continuous semiconductor material, is appropriately laterally divided into a plurality of active regions by appropriate isolation structures 102C, such as shallow trench isolations. As discussed above, the transistors 150A, 150B, 150C may represent highly complex semiconductor devices in which superior performance and reduced lateral dimensions are required so that the gate electrode structures 160A, 160B, 160C may be provided with a gate length of 40 nm and less, depending on the overall process and device requirements. It should be appreciated that the gate length is to be understood according to the sectional view of FIG. 1 as the horizontal extension of a gate electrode material 163 formed on a gate dielectric material 161, which separates the electrode material 163 from a channel region 151. Furthermore, the gate electrode structures 160A, 160B, 160C typically comprise a spacer structure 165 and, in this manufacturing stage, a dielectric cap layer or layer system 164 in order to efficiently confine the sensitive materials 163 and 161. As explained above, the gate dielectric material 161 may typically comprise a high-k dielectric material, for instance in the form of hafnium oxide and the like, possibly in combination with a conventional silicon oxide material, silicon oxynitride material and the like. Furthermore, frequently, a metal-containing electrode material (not shown) may be formed on or above the gate dielectric layer 161, for instance in order to provide the required work function of the gate electrode structures 160A, 160B, 160C.
In this manufacturing stage, the active region 102A comprises a threshold voltage adjusting semiconductor material 102B, for instance provided in the form of a silicon/germanium alloy having a germanium concentration of approximately 20-30 atomic percent, depending on the transistor requirements and the thickness of the layer 102B. That is, the finally achieved threshold voltage and other transistor characteristics significantly depend on the material 102B, i.e., on its material composition and layer thickness in combination with other characteristics, such as the configuration of drain and source regions still to be formed in the active region 102A in a later manufacturing stage. Additionally, the device 100 comprises an efficient strain-inducing mechanism on the basis of a silicon/germanium alloy 104 that is provided in respective cavities 103, which are formed in the active region 102A laterally adjacent to the respective gate electrode structures 160A, 160B, 160C. The strain-inducing effect of the silicon/germanium material 104 results from a lattice mismatch of the natural lattice constants of a silicon/germanium material compared to the silicon base material of the active region 102A. That is, the germanium atomic species having a greater covalent radius compared to silicon results, upon forming the cubic face-centered crystalline structure, in a greater lattice constant when the crystalline growth occurs in a non-disturbed manner. When forming the silicon/germanium crystal lattice on a silicon base material, which thus has a reduced lattice constant compared to the silicon/germanium alloy, the growing silicon/germanium material takes on the lattice constant of the underlying base material, thereby resulting in a deformed or strained crystalline material, which in turn may interact with the neighboring channel region 151, thereby inducing a desired compressive strain therein. Basically, the resulting strain may significantly depend on the magnitude of the lattice mismatch between the material 104 and the silicon base material of the active region 102A, wherein the actual strain in the channel region 151 is also significantly determined by the amount of strained silicon/germanium material, i.e., by the depth and shape of the cavity 103 and by the proximity of the cavity and thus the material 104 with respect to the channel region 151. Generally, it would, therefore, be preferable to provide the material 104 with reduced offset from the channel region 151 and with a high germanium concentration in order to increase the lattice mismatch and thus the resulting degree of lattice deformation and thus strain. It turns out, however, that simply increasing the germanium concentration does not necessarily result in superior transistor performance since many other aspects may also significantly contribute to the finally obtained transistor characteristics. For example, lattice defects may occur, in particular at the interface between the silicon base material and the strained semiconductor material 104, wherein the defect density may significantly increase with an increasing germanium concentration in the material 104. Furthermore, during the further processing, a pronounced difference in processing silicon material compared to a silicon/germanium material having a high germanium concentration may also contribute to process non-uniformities, for instance when forming a metal silicide in drain and source regions still to be formed and the like, which may thus also negatively affect the final transistor characteristics. For this reason, frequently a “graded” germanium concentration may be used in the material 104, for instance by providing a deeper portion 104A with a moderately high germanium concentration, for instance up to 30 percent, while an upper portion 104B may have a significantly lower germanium concentration, for instance 20 atomic percent or less. In this manner, many disadvantages associated with a high germanium concentration at a top surface of the device 100 may be avoided or at least significantly reduced by providing the graded configuration of the silicon/germanium alloy 104. On the other hand, upon further reducing the overall device dimensions, it turns out that increasingly a performance degradation as well as pronounced yield losses are observed, which are believed to be caused, on the one hand, by the presence of a silicon/germanium material of typically three different germanium concentrations, i.e., the threshold voltage adjusting material 102B, the first portion 104A and the second portion 104B of the strain-inducing semiconductor material 104, and, on the other hand, by undue effects of processes such as cleaning processes to be performed upon fabricating the device 100, as will be discussed later on in more detail.
In view of the former aspect, it is assumed that the threshold voltage adjusting semiconductor material 102B, which may have a germanium concentration of typically 20-30 atomic percent, may negatively affect the strain conditions in the channel region 151, in particular when the germanium concentration differs from the germanium concentration in the portions 104B and 104A. For example, in a critical zone 105, silicon/germanium materials of three different material compositions may have to be grown on the silicon base material, thereby resulting in a pronounced degree of defects, such as dislocations and the like, which may reduce the finally achieved compressive strain in the channel region 151.
With respect to the latter aspect affecting the processing and thus the final performance of the transistors 150A, 150B, 150C, it is to be noted that, during many critical process phases, appropriate etch chemistries or cleaning chemistries, such as hot APM (ammonium and hydrogen peroxide mixture) have to be applied, for instance upon removing a portion of the spacer structure 165 and the like, wherein the critical zone 105 may have a reduced etch resistivity, which may, therefore, result in the pronounced etch attack, which in turn may compromise integrity of sensitive materials in the gate electrode structures 160A, 160B, 160C or which may generally result in a device deterioration due to a threshold voltage shift and the like.
Generally, the device 100 can be fabricated on the basis of any appropriate process strategy. For example, the active region 102A may be formed by appropriately dimensioning and forming the isolation structure 102C, which in turn is typically accomplished by applying sophisticated lithography, etch, deposition, anneal and planarization techniques. Thereafter, the basic electronic characteristics of the active region 102A are adjusted, for instance, by applying implantation processes and using an appropriate masking regime. Next, the threshold voltage adjusting semiconductor alloy 102B is selectively formed on active regions in which the adjustment of the threshold voltage requires an adaptation or a shift of the band gap energy with respect to other active regions, such as the active regions of N-channel transistors and the like. To this end, typically, an appropriate hard mask material is provided so as to cover other active regions and expose, for instance, the active region 102A to a selective epitaxial growth ambient in which process parameters are selected in compliance with well-established process recipes so as to achieve the deposition of the silicon/germanium material on exposed crystalline silicon surface areas, while a pronounced material deposition on dielectric surface areas such as the cap layers 164, the spacer structures 165 and the isolation regions 102C is suppressed. Thereafter, any hard mask materials from other active regions are removed and the processing is continued by forming gate electrode structures, such as the structures 160A, 160B, 160C. To this end, appropriate materials are formed, for instance, by deposition, wherein, as discussed above, a high-k dielectric material is typically provided in combination with appropriate metal-containing electrode materials, such as titanium nitride and the like, in order to obtain a desired confinement of the sensitive high-k dielectric material and also provide an appropriate work function. To this end, it is frequently necessary to incorporate an additional metal species, such as aluminum and the like, into the metal-containing electrode material and/or into the dielectric layer 161, which may be accomplished by applying appropriate heat treatments and the like. Thereafter, typically, a further electrode material is deposited, such as a polysilicon material and the like, followed by the deposition of any further hard mask materials and cap materials as required. Next, complex lithography and etch techniques are applied in order to form the gate electrode structures 160A, 160B, 160C with the desired critical dimensions. Thereafter, a liner material (not shown) is typically formed, for instance as a silicon nitride material, so as to confine any sensitive materials of the gate electrode structures on sidewalls thereof, followed by the formation of the spacer structure 165, which may in other device areas be used as a mask layer during a process sequence in which the cavities 103 may be selectively formed in the active region 102A, followed by the selective epitaxial deposition of the material 104. To this end, well-established process techniques are applied for forming the cavities 103, followed by a selective deposition sequence for forming the materials 104A, 104B, wherein process parameters such as the gas flow rate of a germanium-containing precursor gas are appropriately adjusted in order to obtain a desired graded germanium concentration, as discussed above. Thereafter, in some strategies, the spacer structure 165, acting as an offset spacer for defining the lateral offset of the cavities 103, may be removed, which may include the application of efficient chemical recipes which, as discussed above, may result in pronounced damage, in particular in the zone 105, due to the reduced etch resistivity.
Consequently, the further processing has to be continued on the basis of a degraded device configuration, in particular within the critical zone 105, thereby also affecting the overall transistor characteristics, such as threshold voltage and the like, while also a significant reduction of the production yield is observed upon completing the transistors 150A, 150B, 150C by forming drain and source regions and the like.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which sophisticated transistors may be formed on the basis of an embedded strain-inducing semiconductor material, while avoiding or at least reducing the effects of one or more of the problems identified above.